1. Field of the Invention
The present invention relates to a termination structure for semiconductor devices, especially, high breakdown voltage semiconductor devices (such as diodes, IGBTs or MOSFETs) used in power converters or the like.
2. Description of the Related Art
High breakdown voltage discrete power devices play a central role in power converters. The devices include elements such as insulated gate bipolar transistors (IGBTs), and metal oxide semiconductor field-effect transistors (MOSFETs). Each of the devices consists of an active portion which controls a current, and a termination structure (or edge structure) which ensures breakdown voltage. Although it is a matter of course that the breakdown voltage of an ideal termination structure is higher than that of the active portion, the breakdown voltage of the termination structure must endure the influence of external ions. For example, a discrete element formed in such a manner that a power semiconductor chip is sealed with a resin is a form type of power semiconductor device (IGBT, MOSFET, diode, etc.) products. A power module formed in such a manner that a power semiconductor chip is housed in a housing or a power semiconductor chip and a control circuit chip are housed in a housing is another form type. External ions always exist in a peripheral environment of power converters using these power semiconductor devices. The external ions come from a sealing material (gel, epoxy resin, etc.) used in packages of these discrete elements or power modules and reach a surface of a termination structure. The external ions which have reached the surface of the termination structure pass through a passivation layer of the device and reach an upper portion of a silicon region of the device to cause deterioration of the breakdown voltage of the termination portion. Accordingly, not only the module/package material and the passivation material of the element must have functions of suppressing the influence of external ions but also the configuration of the termination structure region per se must be designed as a structure capable of suppressing the influence of external charge (external ions), that is, to have resistance thereto.
A guard ring structure (hereinafter simply referred to as guard ring structure) flanked with conductive field plate has been heretofore used widely as a termination structure. For example, the guard ring structure has been disclosed in B. Jayant Baliga “Fundamentals of Power Semiconductor Devices” (US), first edition, Springer Science+Business Media, 2008, p. 137. FIG. 41 is a sectional view showing the guard ring structure. A p+ guard ring 20a which is connected to an emitter electrode 11 and p+ guard rings 20b to 20f which are not connected to the emitter electrode 11 so as to be electrically floating are formed in a termination structure region 33. A channel stopper layer 6 is formed at an outer circumferential end of the device (at a right end of the termination structure region 33 in FIG. 41) so as to be distant from the p+ guard ring 20f. Conductive field plates 21a to 21e are connected to the p+ guard rings 20b to 20f respectively and a field plate (stopper field plate 15) of the channel stopper layer 6 is connected to the channel stopper layer 6. This field plate-including guard ring structure has excellent characteristic in charge resistance because the influence of external charge coming from the outside on electric characteristic is a little. In the termination structure region 33, silicon oxide films such as separation oxide films 2 or interlayer insulating films 8 formed on a surface are covered with the field plates 21a to 21e to thereby prevent movement of an equipotential surface generated when external charge reaches the vicinity of the oxide films. Moreover, because potential in the vicinity of each of the p+ guard rings 20a to 20f follows the equipotential surface distribution of a depletion layer spread inside silicon, potential of each of the p+ guard rings 20a to 20f per se is stable. Because the stable potential determines potential of each of the field plates 21a to 21e, the silicon oxide film exposed from the surface of the termination structure region is prevented more sufficiently from being affected by external charge.
A structure for preventing more sufficiently the influence of external charge coming from the outside has been disclosed in U.S. Pat. No. 6,445,054 (FIG. 42). When external charge is present in the surface of the termination structure region 33, charge is induced between the surface of the n-type drift layer 1 confronting the separation oxide film 2 and the separation oxide film 2 and between the surface of the n-type drift layer 1 and the interlayer insulating film 8. The n-channel stopper layer 6 equipotential to a collector electrode 14 is electrically connected to the emitter electrode 11 by the charge, so that a large leakage current is generated or the breakdown voltage is deteriorated. To prevent the electrical connection, n-type channel stopper layers 23 higher in concentration than the n-type drift layer are formed so as to be adjacent to the active region sides of the p+ guard rings 20b to 20f, respectively. Similarly, p-type channel stopper layers 22 are formed so as to be adjacent to the device outer circumferential sides of the p+ guard rings 20a to 20f, respectively. For example, when positive external charge comes into the surface of the termination structure region, an electron storage layer where electrons are stored as negative charge is formed in an SiO2/Si interface of the n-type drift layer 1. Therefore, electrical connection between the collector electrode and the emitter electrode by the electron storage layer is suppressed by the p-type channel stopper layers 22. On the other hand, when negative external charge comes into the surface of the termination structure region, a hole storage layer where holes are stored as positive charge is formed in the SiO2/Si interface of the n-type drift layer 1. Therefore, electrical connection between the collector electrode and the emitter electrode by the hole storage layer is suppressed by the n-type channel stopper layers 23.
On the other hand, a structure shown in FIG. 43 has been disclosed in JP-A-2003-23158 in order to shorten the length of the termination structure region. According to FIG. 43, a RESURF (Reduced Surface Electric Field) layer 38 having a RESURF effect is formed in the termination structure region so as to be adjacent to a p+ layer connected to the emitter electrode 11. The RESURF layer 38 is a layer sufficiently lower in concentration than a general guard ring layer, so that the RESURF layer 38 can have a shorter distance than that of the guard ring structure to relax electric field intensity.
A termination structure dubbed VLD (Variation of Lateral Doping) has been disclosed in JP-A-Sho-61-84830 (FIG. 40). That is, a p-type dopant (such as boron) is imported and diffused into a terminal structure region through a large number of opening portions in the separation oxide film 2. As shown in FIG. 40, lateral diffusion portions of p-type diffusion layers 17a to 17d adjacent to one another overlap with one other. The widths of the opening portions are reduced in a direction of from the chip inner circumferential side to the chip outer circumferential side, and the ratio of each opening portion to the separation oxide film is reduced. Therefore, the p-type diffusion layers 17a to 17d are formed so that both diffusion depth and concentration are reduced in a direction of from the chip inner circumferential side to the chip outer circumferential side. A pn junction between the p-type diffusion layers 17a to 17d and the n-type drift layer 1 is generally formed as a distribution of envelop curves of the p-type diffusion layers 17a to 17d or wavy curves based on the envelope curves. The aforementioned termination structure shown in FIG. 40 is called VLD structure. A region where the p-type diffusion layers 17a to 17d overlap with one another is called VLD region 17. Because the lateral diffusion portions of the adjacent p-type diffusion layers 17a to 17d overlap with one another, the length of the termination structure region is substantially equal to the length of the RESURF layer, so that the VLD structure becomes sufficiently shorter than the guard ring structure.
In the aforementioned guard ring structure, the length occupied by the termination structure region in the chip generally becomes large because of the width of each p+ guard ring layer per se and the number of p+ guard ring layers arranged. For this reason, the ratio of the area occupied by the termination structure region in the chip becomes large when the guard ring structure is used for a high breakdown voltage (e.g. 1700 V or higher) device in which the termination structure region must be long inevitably or when the guard ring structure is used for a small current purpose in which the area of a device chip becomes small. As a result, the number of chips fractionated from one silicon wafer is reduced to cause a problem that chip cost increases.
In the RESURF structure, it is necessary to distribute potential of silicon surface (equipotential surface) equally. For this reason, the silicon oxide films cannot be covered with the field plates, so that the equipotential surface distribution shape of the RESURF structure portion varies sensitively according to external charge to thereby lower the breakdown voltage.
In the VLD structure, the concentration of the p-type diffusion layers (hereinafter referred to as VLD region) of the termination structure region can be set to be relatively higher than that of the RESURF structure, so that in this respect, the VLD structure is hardly affected by external charge. However, the stability of the VLD structure is inferior to that of the guard ring structure yet. As described above, when external charge comes flying, the equipotential surface distribution shape in the termination structure region changes. For this reason, the electric field intensity distribution in the vicinity of the semiconductor surface of the termination structure region changes, so that the position of maximum electric field intensity shifts to the chip inner circumferential side or outer circumferential side in accordance with the polarity of external charge. In the case of a p-type VLD structure, the maximum electric field intensity according to positive external charge moves only in the inside of the VLD structure because the depletion layer shifts to the chip inner circumferential side. That is, the VLD structure can absorb the influence of positive external charge. However, one of the maximum electric field intensity maxima according to negative external charges moves to the outer circumferential side of the VLD region because the depletion layer shifts to the chip outer circumferential side. As a result, the electric field intensity in the VLD region is reduced. The voltage allowed to be withstood by the voltage breakdowning structure is a laterally integrated value of electric field intensity. As a result of shifting of the depletion layer, the integrated value in the VLD structure portion is reduced so that the voltage change cannot be absorbed. For this reason, even in the VLD structure, the breakdown voltage according to negative external charge is reduced.